Systems and Methods for Managing Timing Functions in Multiple Timing Protocols

ABSTRACT

One embodiment of the invention includes a master timer controller for a controlling a controller configured to implement a plurality of functions at each of a respective plurality of scheduled times, each of the plurality of scheduled times is converted to a respective plurality of time values associated with a master timing protocol The master timer controller has a plurality of comparators configured to compare the accumulated time value with each of the respective plurality of time values, each of the plurality of comparators being further configured to generate a respective one of the plurality of control signals upon the accumulated value of the master timer being equal to the respective one of the plurality of time values. Another embodiment also includes a method for managing timing functions associating with at least one timing protocol.

CROSS REFERENCE TO RELATED APPLICATION

This application is a Continuation of and claims priority to U.S. Pat.No. 7,944,904 issued on May 17, 2011, filed on Apr. 25, 2007.

TECHNICAL FIELD

Embodiments of the invention relate to electronic circuits, and morespecifically to systems and methods for managing timing functions inmultiple timing protocols.

BACKGROUND

As the demand for electronic devices increases, technology has improvedto provide designs for electronic devices that operate more quickly andefficiently. In a given electronic device, many interconnectedcomponents are designed to operate based on very specific timingrelative to each other. As such, typical electronic devices operateusing timers configured to signal a time to perform one or morefunctions. Some electronic devices, such as wireless universal serialbus (WUSB) transceivers, implement a number of different timersoperating in different timing protocols to control a variety offunctions associated with each of the different timing protocols.

FIG. 1 illustrates an example of a network 10 that implements a varietyof different timing functions. The network 10 includes a host device 12that implements a WUSB communication protocol 14 to act as a wirelesshost in communicating with a wireless device 16, demonstrated in theexample of FIG. 1 as a wireless mouse. The host device 12 can be acomputer, or can be any of a variety of other networked devices. As anexample, a printer on a wireless network can act as a host for a digitalcamera via a wireless channel. In the example of FIG. 1, the host device12 can also implement the WUSB communication protocol 14 to communicatewith any of a variety of other wireless devices 16, as well, such as awireless hard-drive and/or a wireless camera. The host device 12 and thewireless device 16 wirelessly communicate on a wireless channel 18 thatincludes communication packets configured in the WUSB communicationprotocol 14.

The WUSB communication protocol 14 includes a transaction timer 20. Thetransaction timer 20 is a timer that typically increments in a time baseof approximately 1 μs, and thus has a frequency of approximately 1 MHz.The transaction timer 20 is configured to control timing associated withthe host device 12 to send control packets called micro-scheduledmanagement command (MMC) packets to the wireless device 16 and totransmit and receive data packets and/or other types of packets (e.g.,handshaking and/or notification packets) from the wireless device 16.Upon transmitting an MMC packet, the host device 12 resets thetransaction timer 20 to zero and sets a scheduled time to perform afunction based on an accumulated value of the transaction timer 20. Asan example, the scheduled time could be a scheduled time for thecomputer 12 to transmit a data packet to the wireless device 16, or toactivate its receiver to receive a data packet from the wireless device16. In a similar manner, upon receiving the MMC packet, the wirelessdevice 16 can reset its own transaction timer to zero and can set ascheduled time based on a timestamp that is included in the MMC packet.For example, the scheduled time could be a scheduled time for thewireless device 16 to transmit a data packet, or could be a scheduledtime for the wireless device 16 to receive a data packet from anotherdevice on the network, such that the scheduled time indicates a time atwhich the wireless device 16 is to enable its wireless receiver. Thetime for transmission of an MMC packet from the host device 12 istypically required to be very accurate (e.g., ±40 ns) to compensate fordelay times associated with the interactions between a media-accesscontrol (MAC) layer on which the transaction timer 20 resides and aphysical (PHY) layer from which packets are transmitted on the wirelesschannel 18.

The WUSB communication protocol 14 also includes a WUSB channel timer22. Like the transaction timer 20, the WUSB channel timer 22 is a timerthat typically increments in a time base of approximately 1 μs, and thushas a frequency of approximately 1 MHz. However, unlike the transactiontimer 20, the WUSB channel timer 22 is free-running, such that it doesnot reset to zero in response to other functions and events. The WUSBchannel timer 22 is typically implemented to synchronize the time baseof the wireless device 16 with the host device 12. For example, the hostdevice 12 can provide a reference timestamp in the WUSB channel timeprotocol that is adjusted for MAC-layer and PHY-layer interactions andother delays in an MMC packet that is transmitted to the wireless device16. Thus, because the reference timestamp is adjusted for time delays,the wireless device 16 can update an internal WUSB channel timer withthe timestamp and begin incrementing its internal WUSB channel timer atsubstantially the same rate as the WUSB channel timer 22, such that eachof the host device 12 and the wireless device 16 have substantiallysynchronized WUSB channel timers. Therefore, the wireless device 16 canimplement its internal WUSB channel timer to accurately schedule timesfor transmission of packets to the host device 12 via the wirelesschannel 18. Because the WUSB channel timer 22 is typically implementedas a free-running timer, it is typically required to have a very largerange. Accordingly, the WUSB channel timer 22 is implemented as a 24-bittimer, with bits 0-7 counting in microseconds (i.e., from 0-124) andbits 8-23 counting in ⅛^(th) milliseconds.

In the example of FIG. 1, the network 10 also includes a set-top box 24that is coupled to a media device 26, demonstrated in the example ofFIG. 1 as a digital television. The set-top box 24 is wirelessly coupledto the host device 12 via the wireless channel 18. However, in theexample of FIG. 1, the set-top box 24 communicates with the host device12 via internet protocol (IP). Thus, in addition to WUSB protocol 14,the host device 12 also includes a WiMedia MAC communication protocol 28configured to interact with the WUSB communication protocol 14 and oneor more other communication protocols to time schedule communications ina time-division multiplexed (TDM) manner over the wireless channel 18.Although the example of FIG. 1 demonstrates that the WUSB communicationprotocol 14 and the WiMedia MAC communication protocol 28 are separate,the WUSB communication protocol 14 can be considered as operating overthe WiMedia MAC communication protocol 28.

The WiMedia MAC communication protocol 28 implements a superframe timer30 to provide shared communication between the WUSB communicationprotocol 14 and IP over the wireless channel 18. The superframe timer 30can be a 16-bit timer that, like the transaction timer 20 and the WUSBchannel timer 22, can typically increment in a time base ofapproximately 1 μs, and thus has a frequency of approximately 1 MHz.Therefore, the superframe timer 30 can define a single superframe of65,536 microseconds in which the WUSB communication protocol 14 and IPare TDM divided. Upon power-up of the host device 12, the WiMedia MACcommunication protocol 28 can begin a superframe based on the lastreceived beacon of the wireless device 16 and the set-top box 24. Assuch, the WiMedia MAC communication protocol 28 synchronizes superframetimers of the set-top box 24 and the wireless device 16 with thesuperframe timer 30, such that all of the superframe timers aresynchronized with the slowest device beacon. The WiMedia MACcommunication protocol 28 can thus schedule packet transmission times onthe PHY-layer using the superframe timer 30 on the MAC layer.Accordingly, the WUSB communication protocol 14 and IP can occupy thesame wireless channel 18 without interfering with each other.

Because of the very specific functionality of the transaction timer 20,the WUSB channel timer 22, and the superframe timer 30, each of thesetimers is implemented in a different timing protocol. As a result, thehost device 12 and the wireless device 16 may include three separatehardware timing circuits to implement each of the three timers. Inaddition, each of the three hardware timing circuits are implementedfrom a clock signal that is specific to the timing operations, such thatadditional clock hardware for generating the clock signal and for clockedge-synchronization is required. Thus, the hardware that is required toimplement the timers occupies additional space, results in added cost,and consumes more power. Furthermore, implementing the three separatetimers in three separate timing protocols, such that each requires adedicated hardware timing circuit, is inflexible in that additionaltimers and related functions that are subsequently needed would likewiserequire dedicated timing circuitry at an additional cost.

SUMMARY

One embodiment of the present invention includes a system for managingtiming functions associating with at least one timing protocol. Thesystem comprises a controller configured to implement a plurality oftiming functions at each of a respective plurality of scheduled times.The system also comprises a time protocol converter configured toconvert each of the plurality of scheduled times to a respectiveplurality of time values associated with a master timing protocol. Thesystem further comprises a master timer controller configured togenerate a plurality of control signals associated with the plurality oftiming functions based on an accumulated value of a master timerassociated with the master timing protocol relative to the plurality oftime values.

Another embodiment of the present invention includes a method formanaging a plurality of timing functions associated with a plurality oftiming protocols. The method comprises generating a plurality ofreference time values in a master timing protocol in response to arespective plurality of stimulus signals. Each of the plurality ofstimulus signals can be configured to invoke at least one of theplurality of timing functions. The method also comprises generating aplurality of offset time values in the master timing protocol relativeto each of the respective plurality of reference time values. The methodfurther comprises activating a control signal associated with the atleast one of the plurality of timing functions upon an accumulated timevalue of a master timer in the master timing protocol being equal toeach of a plurality of scheduled time values that are equal to a sum ofthe respective plurality of offset time values relative to therespective plurality of reference time values.

Another embodiment of the present invention includes a communicationsystem. The communication system comprises means for implementing aplurality of timing functions associated with a plurality ofcommunication packets at a respective plurality of scheduled timevalues. The communication system also comprises means for generating aplurality of reference time values associated with the communicationpackets in a master timing protocol. The communication system alsocomprises means for converting the plurality of scheduled time values tothe master timing protocol relative to the respective plurality ofreference times values. The method further comprises means forgenerating a plurality of control signals corresponding to the pluralityof timing functions associated with the communication packets based on amaster timer associated with the master timing protocol relative to theconverted plurality of scheduled time values.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a prior art network implementingvarious communications protocols.

FIG. 2 illustrates an example of a timer system in accordance with anaspect of the invention.

FIG. 3 illustrates another example of a timer system in accordance withan aspect of the invention.

FIG. 4 illustrates an example of a network in accordance with an aspectof the invention.

FIG. 5 illustrates an example of a method for implementing a singletimer for multiple timing protocols in accordance with an aspect of theinvention.

DETAILED DESCRIPTION

The present invention relates to electronic circuits, and morespecifically to a single timer for managing timing functions in multipletiming protocols. A high-frequency clock is provided as an input to amaster timer that is configured as a free-running, high-frequency timerin a master timing protocol. A controller provides scheduled timescorresponding to functions to be implemented at specific times. Thescheduled times are configured as offsets relative to reference timevalues that are static time values of the master timer latched atspecific times based on one or more stimulus signals. The stimulussignals can include, for example, one or more signals provided from thecontroller in response to an event from which a scheduled time is to beperformed, such as the arrival of a packet in a communication system.The reference time values and the scheduled times are provided to a timeprotocol converter that is configured to convert the scheduled times tothe master timing protocol relative to the reference time values. Uponan accumulated value of the master timer being equal to a convertedscheduled time, a control signal, such as an interrupt or an enablesignal, is generated corresponding to an associated timing function.Thus, a single timer can be implemented to manage a plurality ofunrelated timing functions.

FIG. 2 illustrates an example of a timer system 50 in accordance with anaspect of the invention. The timer system 50 in the example of FIG. 2can be included in any of a variety of computing and/or communicationsdevices that implements one or more timers. As an example, the timersystem 50 can be included in a wireless device and/or a wireless hostdevice in a wireless universal serial bus (WUSB) network, such that thetimer system 50 can be configured to replace at least one of atransaction timer, a WUSB channel timer, and a superframe timer, as isdescribed in greater detail in the example of FIG. 4 below.

The timer system 50 includes a controller 52 that is configured toimplement a plurality of timing functions. As an example, the controller52 can form at least a portion of firmware configured to transmit andreceive communications signals at specific predetermined times. Thetiming functions can be triggered by one or more control signals 54received by the controller 52, demonstrated in the example of FIG. 2 asCTRL_SIGS. For example, the control signals 54 can include interrupts,enable signals for a transceiver to transmit and/or receive acommunication packet, or any of a variety of other signals. The timingfunctions can also be triggered independently of external signalsprovided to the controller 52, such as periodic timing functions of thecontroller 52.

To implement the timing functions, the controller 52 is configured togenerate a plurality of scheduled times 56, demonstrated in the exampleof FIG. 2 as N scheduled time signals labeled TIME_1 through TIME_N,where N is a positive integer. The plurality of scheduled times 56 caneach correspond to a timing function, such that the plurality ofscheduled times 56 are future times at which the respective timingfunctions are to be performed. Each of the scheduled times 56 couldcorrespond to one or more of the control signals 54 provided to thecontroller 52. As an example, one of the control signals 54 could be asignal that activates a receiver (not shown) to receive a control packetto which the controller 52 is required to respond. Thus, the scheduledtime TIME_1 could be a time at which the controller 52 is required totransmit a corresponding control packet.

As another example, a control packet transmitted from a wireless hostcould prompt a wireless device to provide a responsive packet. The timefor which the responsive packet is required to be sent could be includedas a time-stamp in the received command packet, such as a transactiontime for a WUSB device to send a data packet in response to amicro-scheduled management command (MMC) packet. Thus, if the timersystem 50 is included in a wireless host, the controller 52 can providethe time in the time-stamp as a given one of the scheduled times 56. Asa result, the scheduled times 56 could be times that are in any of avariety of timing protocols that could be separate and independent ofeach other.

The controller 52 provides the scheduled times 56 to a time protocolconverter 58 and a signal STIMULI to a master timer controller 60. Themaster timer controller 60 includes a master timer 62 that is controlledby a high-frequency clock, demonstrated in the example of FIG. 2 as thesignal FAST_CLK. The master timer 62 may be configured to have agranularity based on the frequency of the signal FAST_CLK that is smallenough to account for the most accurate timing function implemented bythe controller 52. In addition, the master timer 62 can be afree-running timer having a number of bits that is a function of thefrequency of the signal FAST_CLK and a timing function having thelongest repeatable time domain cycle that is implemented by thecontroller 52. Because the master timer 62 is configured to have agranularity and a time domain cycle that accounts for the most accuratetiming function and the timing function having the longest repeatabletime domain cycle, respectively, the master timer 62 thus defines amaster timing protocol.

As an example, for the timer system 50 being implemented in a WUSBnetwork similar to as described above in the example of FIG. 1, a timefor transmission of an MMC packet is typically required to be veryaccurate (e.g., ±40 ns) to compensate for delay times associated withthe interactions between a media-access control (MAC) layer and aphysical (PHY) layer, as well as the strict timing requirements for WUSBtransactions. Thus, the master timer 62 can be configured to incrementat least 40 MHz to achieve an appropriate granularity for the accuratetransmission time that is necessary for WUSB transactions and MMC packettransmissions. In addition, a WUSB channel timer in a WUSB network is a24 bit timer with bits 8-23 counting in ⅛^(th) milliseconds, and thusincludes a repeatable 16-bit 118^(th) millisecond granularity timer.Therefore, the WUSB channel timer can be the longest repeatable timedomain cycle relative to a transaction timer and a superframe timer.Accordingly, for a master timer 62 controlled by a signal FAST_CLKhaving a frequency of 40 MHz, the master timer 62 can require at least30 bits to represent an entire cycle of a WUSB channel timer.

The time protocol converter 58 is configured to convert the scheduledtimes 56 to scheduled time values 64, labeled CVT_TIME_1 through CVT_TIME_N, configured in the master timing protocol. The master timercontroller 60 provides a plurality of reference times 66 as inputs tothe time protocol converter 58, the reference times 66 beingdemonstrated in the example of FIG. 2 as REF_TIME_1 through REF_TIME_N.The reference times 66 can be configured in the master timing protocol,and each of the reference times 66 can correspond to a given one of thescheduled times 56. As an example, each of the reference times 66 can bea static time value in the master timing protocol, such that each of thereference times 66 can be time values that are latched from the mastertimer 62 at specific times as designated by the signal STIMULI providedfrom the controller 52. Therefore, the time protocol converter 58converts a given scheduled time 56 to the master timing protocol togenerate a respective converted scheduled time 64 that is an offsetrelative to the respective reference time 66.

Each of the converted scheduled time values 64 are provided to themaster timer controller 60. The master timer controller 60 is configuredto generate a plurality of control signals 68 corresponding to each ofthe respective converted scheduled time values 64 based on the mastertimer 62, the control signals 68 being demonstrated in the example ofFIG. 2 as CTRL_SIG_1 through CTRL_SIG_N. Specifically, for a given oneof the converted scheduled time values 64, the master timer controller60 generates a respective one of the control signals 68 in response toan accumulated value of the master timer 62 being equal to the given oneof the scheduled time values 64.

The control signals 68 each correspond to the timing function for whichthe given scheduled times 56 were generated by the controller. As anexample, the control signals 68 can include interrupts and/or enablesignals for firmware and/or software implementation. Thus, the controlsignals 68 can be provided to the controller 52 to implement therespective timing function, or to generate another scheduled time 56,such that one or more of the control signals 68 can be provided as or inaddition to the control signals 54. In addition, one or more of thecontrol signals 68 can be provided to other components (not shown) in acomputer or communication device in which the timer system 50 isincluded, such that the other components can perform the scheduledtiming functions corresponding to the respective control signals 68.

In the example of the timer system 50 being implemented in a wirelessdevice in a WUSB network, a packet received at the PHY-layer, such as anMMC packet, could include a time stamp that indicates a scheduledtransaction time at which the controller 52 is required to provide anacknowledgement (e.g., a responsive packet or a data packet). Typically,as described above in the example of FIG. 1, the controller 52 wouldreset a transaction timer upon receiving the MMC packet and wouldtransmit the acknowledgement upon the accumulated value of thetransaction timer reaching the scheduled time provided in the timestamp. Thus, in the example of FIG. 2, the controller 52 would assertthe signal STIMULI to latch a static time of the master timer 62, whichis provided as one of the reference times 66 to the time protocolconverter 58.

As an example, the controller 52 can also provide a scheduledtransaction time that is time stamped in the MMC packet as one of thescheduled times 56 to the time protocol converter 58. Therefore, thetime protocol converter 58 converts the scheduled transaction time tothe master timing protocol relative to the reference time 66 that islatched from the master timer 62 upon the PHY-layer receiving thepacket. As such, the signal STIMULI can be asserted at the beginning ofa received packet and/or at the end of a received packet for subsequenttransmission of a packet relative to the timing of the received packet.For example, the time protocol converter 58 can convert the scheduledtransaction time from microseconds to the granularity of the mastertimer 62 (e.g., 1/40 MHz) and add it to the reference time 66corresponding to the scheduled transaction time 56 to generate theconverted scheduled time value 64 in the master timing protocol.Accordingly, the converted scheduled time value 64 in the master timingprotocol is an offset time relative to the reference time 66 in themaster timing protocol, such that the controller 52 can transmit apacket upon an accumulated value of the master timer 62 being equal tothe converted scheduled time value 64.

It is to be understood that the timer system 50 is not intended to belimited to the example of FIG. 2. For example, although the timeprotocol converter 58 is demonstrated in the example of FIG. 2 as anindependent component, it is to be understood that the time protocolconverter 58 could be configured as a software routine residing in thecontroller 52, or as a combination of software and firmware configuredto interact with each other to convert the scheduled times 56 into theconverted scheduled time values 64. In addition, it is to be understoodthat the time protocol converter 58 can compensate for rollover in themaster timer 62, as well as delays in converting the scheduled times 56to the converted scheduled time values 64 by subtracting delay amountsfrom the converted scheduled time values 64. As an example, the delayscan include delays in interaction of the MAC-layer and the PHY-layerand/or computational and processing delays. Furthermore, the timeprotocol converter 58 may be configured to provide one or more of theconverted scheduled time values back to the controller 52, instead of tothe master timer controller 60 for assertion of one or more controlsignals 68. For example, the controller 52 may include one or more ofthe converted scheduled time values 64 in a time stamp in a controlpacket, such as an MMC packet in a WUSB network, that is transmitted toa wireless device (not shown), such that the timing function is to beperformed by the wireless device and not the controller 52. Accordingly,the timer system 50 can be configured in any of a variety of differentways.

FIG. 3 illustrates another example of a timer system 100 in accordancewith an aspect of the invention. The timer system 100 includes a timeprotocol converter 102 and a master timer controller 104. The timeprotocol converter 102 and the master timer controller 104 can beconfigured substantially similarly to the time protocol converter 58 andthe master timer controller 60 in the example of FIG. 2. Therefore,reference will be made to the example of FIG. 2 in the discussion of theexample of FIG. 3.

Similar to as described above regarding the example of FIG. 2, the timeprotocol converter 102 is configured to convert scheduled times 106,labeled TIME_1 through TIME_N, to scheduled time values 108, labeledCVT_TIME_1 through CVT_TIME_N, where N is a positive integer, configuredin the master timing protocol. The scheduled times 106, and thus theconverted scheduled time values 108, can each correspond to a timingfunction, such that they can be future times at which the respectivetiming functions are to be performed. The scheduled time values 108 areprovided to the master timer controller 104, similar to as describedabove in the example of FIG. 2.

The master timer controller 104 includes a master timer 110 that iscontrolled by a high-frequency clock, demonstrated in the example ofFIG. 3 as the signal FAST_CLK. Similar to as described above regardingthe example of FIG. 2, the master timer 110 may be configured to have agranularity based on the frequency of the signal FAST_CLK that is smallenough to account for the most accurate timing function implemented byan associated controller. In addition, the master timer 110 can be afree-running timer having a number of bits that is a function of thefrequency of the signal FAST_CLK and a timing function having thelongest repeatable time domain cycle. Therefore, the master timer 110defines the master timing protocol.

The master timer controller 104 also includes a time latch 112 that iscoupled to the master timer 110. The time latch 112 receives one or morestimulus signals, such as provided by a controller, demonstrated in theexample of FIG. 3 as a signal STIMULI. Upon assertion of the signalSTIMULI, the time latch 112 latches a current static time value of themaster timer 110 and provides the current static time value of themaster timer 110 to the time protocol converter 102 as a reference time,demonstrated in the example of FIG. 3 as REF_TIME. Substantiallyconcurrently, a scheduled time 106 is also provided to the time protocolconverter 102 that corresponds to the reference time REF_TIME.Therefore, the time protocol converter 102 can convert the schedule time106 to one of the scheduled time values 108 relative to the referencetime REF_TIME. Accordingly, the respective converted scheduled time 108is an offset relative to the respective reference time REF_TIME.

Unlike the example of FIG. 2, the example of FIG. 3 demonstrates only asingle reference time REF_TIME provided from the master timer controller104 to the time protocol converter 102. As described above in theexample of FIG. 2, the controller 52 generates the scheduled times asfuture times at which respective timing functions are to be performed inresponse to command signals provided to the controller. The scheduledtimes 106 can thus be generated sequentially. As such, the singlereference time REF_TIME is demonstrated as such in the example of FIG. 3to illustrate that the time latch 112 is activated by the signal STIMULIto latch the current static time value of the master timer 110 atsubstantially the same time that a given one of scheduled times 106 issequentially generated. Accordingly, each time a scheduled time 106 isgenerated, the signal STIMULI is asserted to activate the time latch 112to generate a reference time REF_TIME for the generated scheduled time106.

The scheduled time values 108 are input to a respective plurality ofmemory registers 114 in the master timer controller 104. The memoryregisters 114 can be included in one or more memory modules, such as astatic random access memory (SRAM). Each of the memory registers 114 iscoupled to a comparator 116 that is also coupled to the master timer110. Each of the comparators 116 thus compares the converted scheduledtime values 108 stored in the memory registers 114 with the accumulatedvalue of the master timer 110. Upon the accumulated value of the mastertimer 110 being equal to one of the converted scheduled time values 108,the respective one of the comparators 116 provides one of a plurality ofcontrol signals 118 as an output, the control signals 118 beingdemonstrated in the example of FIG. 3 as CTRL_SIG_1 through CTRL_SIG_N.

The control signals 118 can each correspond to the timing function forwhich the given scheduled times 106 were generated. The control signals118 can include interrupts and/or enable signals for firmware and/orsoftware implementation. As an example, one of the control signals 118can be an interrupt to begin a superframe, one of the control signals118 can activate a transceiver to transmit or receive a packet, one ormore of the control signals 118 can be provided to a controller toimplement a timing function or to generate a scheduled time, one or moreof control signals 118 can be provided to a logic circuit thatimplements the signal STIMULI, and/or one or more of the control signals118 can be provided to other components in a computer or communicationdevice in which the timer system 100 is included. Thus, the controlsignals 118 can be configured in any of a variety software and/orfirmware applications that implement timing functions.

It is to be understood that the timer system 100 is not intended to belimited to the example of FIG. 3. For example, the memory registers 114may be configured in a memory module separate from the master timercontroller 104, such as in active RAM of the computer or communicationdevice in which the timer system 100 is included. In addition, similarto as described above in the example of FIG. 2, it is to be understoodthat the time protocol converter 102 can be implemented as a softwareroutine, and can compensate for rollover in the master timer 110, aswell as delays in converting the scheduled times 106 to the convertedscheduled time values 108. Furthermore, the signal STIMULI may not beasserted based solely on a timing function. For example, the signalSTIMULI can be asserted to latch the static time value of the mastertimer 110 automatically in response to predetermined conditions, withonly a portion of the conditions being important for timing functions.Therefore, the time protocol converter 102 can be configured toassociate only the appropriate reference times REF_TIME with thescheduled times 106 to which they correspond.

FIG. 4 illustrates an example of a network 150 in accordance with anaspect of the invention. The network 150 includes a host device 152having a controller 154 and a transceiver 156. The host device 152 canbe a computer, or can be any of a variety of other networked devices.The controller 154 can be a communications controller configured toassemble packets and provide them to the transceiver 156 fortransmission, and to disassemble communication packets that are receivedvia the transceiver 156. In the example of FIG. 4, the controller 154implements a WUSB communication protocol 158 to act as a wireless hostin communicating with a wireless device 160. As an example, the wirelessdevice 160 can be a wireless mouse, printer, hard-drive, and/or camera.The wireless device 160 likewise includes a controller 161 thatimplements the WUSB communication protocol 158. The controller 154 andthe controller 161 communicate on a wireless channel 162 that includescommunication packets configured in the WUSB communication protocol 158.

The controller 154 also includes a WiMedia MAC communication protocol164, such that the controller 154 can provide wireless communications toand from other devices via a communication protocol other than the WUSBcommunication protocol 158. For example, the network 150 could alsoinclude a set-top box (not shown) that is coupled to a media device,such as a digital television. The set-top box could be wirelesslycoupled to the transceiver 156 via the wireless channel 162, but couldcommunicate with the controller via a communication protocol other thanthe WUSB communication protocol 158, such as internet protocol (IP).Thus, the WiMedia MAC communication protocol 164 is configured tointeract with the WUSB communication protocol 158 and one or more othercommunication protocols to time schedule communications in atime-division multiplexed (TDM) manner over the wireless channel 162.

The controller 154 and/or the controller 161 can be configured togenerate scheduled times for the WUSB communication protocol 158 and/orthe WiMedia MAC communication protocol 164. For example, the controller154 may schedule transaction times to control timing associated withsending and receiving packets to and from the wireless device 160. Thetime for transmission of an MMC packet from the host device 152 can berequired to be very accurate (e.g., ±40 ns). As another example, thecontroller 154 may also provide WUSB channel times in a timestamp in theMMC packets, such that the controller 161 can update an internal WUSBchannel timer with the timestamp and begin incrementing its internalWUSB channel timer for timed transmissions back to the host device 152.As another example, the controller 161 can receive an MMC packet fromthe controller 154 and can schedule a transaction time to transmit adata packet based on a timestamp in the MMC packet. As yet anotherexample, the controller 154 may schedule times for assembling asuperframe based on the WiMedia MAC communication protocol 164 toprovide shared communication between the WUSB communication protocol 158and another communication protocol, such as IP, over the wirelesschannel 162. As such, the WUSB communication protocol 158 and IP canoccupy the same wireless channel 162 without interfering with eachother. Similar to as described above in the example of FIG. 1, thesescheduled times are typically implemented with separate hardware timersthat each increment timers in separate timing protocols.

The host device 152 and the wireless device 160 each also include amaster timing protocol 170 that is configured with a master timer 172and a master timer 174, respectively. Each of the master timers 172 and174 can be controlled by high-frequency clocks, and can be configured tohave a granularity based on the frequency of the respectivehigh-frequency clocks. Thus, the granularity of the master timers 172and 174 can be small enough to account for the most accurate timingfunction implemented by the associated controllers 154 and 161, such asthe required accuracy of packet transmission times. In addition, themaster timers 172 and 174 can be free-running timers having a number ofbits that is a function of the frequency of the high-frequency clock anda timing function having the longest repeatable time domain cycle, suchas a WUSB channel timer.

The controller 154 is coupled to the master timing protocol 170, suchthat scheduled times and timestamps in MMC packets can be converted tothe master timing protocol 170, similar to as described above in theexamples of FIGS. 2 and 3. As an example, the controller 154 can converta scheduled time in the master timing protocol to a transaction timeand/or a WUSB channel time and can timestamp it in an MMC packet to betransmitted to the wireless device 160 via the transceiver 156. Asanother example, the controller 154 can assemble timed communications ina superframe based on interrupt signals that are provided in response tospecific times of the master timer 172. In a similar manner, thecontroller 161 is coupled to the master timing protocol 170, as well,such that the controller 161 can receive an MMC packet from thecontroller 154 and convert one or more timestamps in the MMC packet tothe master timing protocol 170. As such, the controller 161 can scheduletransaction times in the master timing protocol 170 to transmit data orhandshaking packets relative to a time in the master timing protocol 170at which the MMC packet was received. The controllers 154 and 161 canthus each implement the respective master timers 172 and 174 as singletimers to manage any of a variety of timing functions in multiple timingprotocols to wirelessly communicate in the WUSB protocol 158 or inanother communication protocol. Additionally, the host device 152 andthe wireless device 160 can each be configured with any of a variety ofother components that can likewise implement the master timers 172 and174 for timing functions, such that the master timing protocol 170 isflexible to provide capability to manage any of a variety timingfunctions.

It is to be understood that the network 150 is not intended to belimited to the example of FIG. 4. For example, several components of thehost device 152 and wireless device 160 have been omitted for the sakeof simplicity of explanation. In addition, the master timing protocol170 is not intended to be limited to use in WUSB communications, but canbe configured for any of a variety of timing applications and/or devicesthat implement one or more timing protocols. As yet another example, itis to be understood that the master timing protocol 170 is not limitedto being the same for both the host device 152 and the wireless device160, but that each could implement different master timers havingdifferent granularities and numbers of bits. Furthermore, the mastertiming protocol 170 may not replace hardware timers configured in othertiming protocols, but can be configured to operate in addition to otherhardware timers, such as a transaction timer, a WUSB channel timer,and/or a superframe timer.

In view of the foregoing structural and functional features describedabove, methodologies in accordance with various aspects of the presentinvention will be better appreciated with reference to FIG. 5. While,for purposes of simplicity of explanation, the methodology of FIG. 5 isshown and described as executing serially, it is to be understood andappreciated that the present invention is not limited by the illustratedorder, as some aspects could, in accordance with the present invention,occur in different orders and/or concurrently with other aspects fromthat shown and described herein. Moreover, not all illustrated featuresmay be required to implement a methodology in accordance with an aspectthe present invention.

FIG. 5 illustrates an example of a method 200 for implementing a singletimer for multiple timing protocols in accordance with an aspect of theinvention. At 202, a plurality of scheduled times are generated. Thescheduled times can correspond to timing functions, and can be futuretimes at which the timing function is to be performed. The scheduledtimes can be generated by a controller in response to one or morecontrol signals and/or timing functions that have occurred. At 204, arespective plurality of reference times are generated in a master timingprotocol corresponding to a master timer. The reference times can eachcorrespond to a respective one of the scheduled times. The master timingprotocol can correspond to a master timer that is a free-running timercontrolled by a high-frequency clock. The master timer can be configuredto have a granularity based on the frequency of the high-frequencyclock, such that the granularity is small enough to account for the mostaccurate timing function implemented by an associated controller, suchas the required accuracy of packet transmission times. The master timercan have a number of bits that is a function of the frequency of thehigh-frequency clock and a timing function having the longest repeatabletime domain cycle. The reference times can be static time values latchedfrom the master timer substantially concurrently with the generation ofthe scheduled times.

At 206, a plurality of offset times are generated in the master timingprotocol for each of the scheduled times and associated reference times.The offset times can be times in the master timing protocol relative tothe reference times that correspond to the scheduled times, in that theoffset time plus the reference time corresponds to the scheduled time inthe master timing protocol. Delays associated with the timing functionsand rollover associated with the master timer can be accounted for inthe offset times. The offset times relative to the reference times canbe stored in a plurality of memory registers. At 208, a respectiveplurality of control signals are generated based on an accumulated valueof the master timer being equal to the offset times relative to thereference times. The control signals can correspond to timing functions,and can include interrupts and/or enable signals for firmware and/orsoftware. The timing functions can include functions associated withwireless communication, such as transmission and or reception of controlpackets.

What have been described above are examples of the present invention. Itis, of course, not possible to describe every conceivable combination ofcomponents or methodologies for purposes of describing the presentinvention, but one of ordinary skill in the art will recognize that manyfurther combinations and permutations of the present invention arepossible. Accordingly, the present invention is intended to embrace allsuch alterations, modifications, and variations that fall within thespirit and scope of the appended claims.

1-20. (canceled)
 21. A master timer controller for a controlling acontroller configured to implement a plurality of functions at each of arespective plurality of scheduled times, each of the plurality ofscheduled times is converted to a respective plurality of time valuesassociated with a master timing protocol, the master timer controllercomprising: a plurality of comparators configured to compare theaccumulated time value with each of the respective plurality of timevalues, each of the plurality of comparators being further configured togenerate a respective one of the plurality of control signals upon theaccumulated value of the master timer being equal to the respective oneof the plurality of time values.
 22. The master timer controller ofclaim 21, wherein the plurality of time values are stored in arespective plurality of memory registers accessible by the master timercontroller.
 23. The master timer controller of claim 21, wherein theplurality of control signals comprises at least one of interrupts andcommunication enable signals.
 24. The master timer controller of claim21, wherein the master timer controller comprises a time latchconfigured to latch a static time value associated with the master timerin response to at least one stimulus signal.
 25. The master timercontroller of claim 24, wherein the static time value corresponds to areference time associated with one of the plurality of functions, andwherein the time protocol converter generates an offset in the mastertiming protocol relative to the static time value associated with eachof the plurality of scheduled times.
 26. The master timer controller ofclaim 24, further comprising a transceiver configured to wirelesslytransmit and receive communication packets, wherein the at least onestimulus signal comprises at least one of receiving a communicationpacket and transmitting a communication packet.
 27. The master timercontroller of claim 26, wherein the plurality of scheduled timescomprises at least one of a scheduled time to transmit a packet, ascheduled time to activate the transceiver to receive a packet, and atime to generate an interrupt.
 28. A method for managing a plurality oftiming functions, the method comprising: associating the plurality oftiming functions with a plurality of timing protocols; generating aplurality of reference time values in a master timing protocol inresponse to a respective plurality of stimulus signals, each of theplurality of stimulus signals being configured to invoke at least one ofthe plurality of timing functions; generating a plurality of offset timevalues in the master timing protocol relative to each of the respectiveplurality of reference time values; and activating a control signalassociated with the at least one of the plurality of timing functionsupon an accumulated time value of a master timer in the master timingprotocol being equal to each of a plurality of scheduled time valuesthat are equal to the respective plurality of offset time valuesrelative to the respective plurality of reference time values.
 29. Themethod of claim 28, wherein generating a plurality of reference timevalues comprises latching static reference time values from the mastertimer in response to the respective plurality of stimulus signals. 30.The method of claim 28, further comprising: wirelessly transmitting andreceiving communication packets; and activating the plurality ofstimulus signals at least one of a beginning and an end of at least oneof a transmitted communication packet and a received communicationpacket.
 31. The method of claim 30, wherein activating a control signalcomprises at least one of wirelessly transmitting a communication packetin response to a control signal, activating a receiver to wirelesslyreceive a communication packet, and generating an interrupt.
 32. Themethod of claim 28, further comprising storing the plurality of adjustedtime values in a respective plurality of memory registers, and whereinactivating the control signal comprises comparing the accumulated timevalue of the master timer with the plurality of scheduled time valuesstored in the respective plurality of memory registers.
 33. A wirelessuniversal serial bus (WUSB) network configured to implement the methodof claim 28.